View ICM7231_8891.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ICM7231, ICM7232
August 1997
Numeric/Alphanumeric Triplexed LCD Display Drivers
Description
The ICM7231 and ICM7232 family of integrated circuits are designed to generate the voltage levels and switching waveforms required to drive triplexed liquid-crystal displays. These chips also include input buffer and digit address decoding circuitry allowing six bits of input data to be decoded into 64 independent combinations of the output segments of the selected digit. The family is designed to interface to modern highperformance microprocessors and microcomputers and ease system requirements for ROM space and CPU time needed to service a display.
Features
* ICM7231 Drives 8 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input in Parallel Format * ICM7232 Drives 10 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input in Serial Format * All Signals Required to Drive Rows and Columns of Triplexed LCD Display are Provided * Display Voltage Independent of Power Supply * On-Chip Oscillator Provides All Display Timing * Total Power Consumption Typically 200W, Maximum 500W at 5V * Low-Power Shutdown Mode Retains Data With 5W Typical Power Consumption at 5V, 1W at 2V * Direct Interface to High-Speed Microprocessors
Ordering Information
PART NUMBER ICM7231BFIJL ICM7231BFIPL ICM7232BFIPL ICM7232CRIPL NOTE: All versions intended for triplexed LCD displays. TEMP. RANGE (oC) -25 to 85 -25 to 85 -25 to 85 -25 to 85 PACKAGE 40 Ld CERDIP 40 Ld PDIP 40 Ld PDIP 40 Ld PDIP NUMBER OF DIGITS 8 Digit 8 Digit 10 Digit 10 Digit INPUT FORMAT Parallel Parallel Serial Serial PKG. NO. F40.6 E40.6 E40.6 E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3161.1
9-19
ICM7231, ICM7232 Pinouts
ICM7231BF (PDIP, CERDIP) TOP VIEW
CS VDISP BP1 BP2 BP3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VDD 39 A2 38 A1 37 A0 36 VSS 35 BD3 34 BD2 33 BD1 32 BD0 31 AN2 30 AN1 29 f8, a8, an28 28 a8, g8, d8 27 b8, c8, an18 26 f7, e7, an27 25 a7, g7, d7 24 b7, c7, an17 23 f6, e6, an26 22 a6, g6, d6 21 b6, c6, an16 DATA CLOCK INPUT VDISP BP1 BP2 BP3 1 2 3 4 5 6 7 8 9
ICM7232AF, BF (PDIP, CERDIP) TOP VIEW
40 VDD 39 WRITE INPUT 38 DATA INPUT 37 DATA ACCEPTED OUTPUT 36 VSS 35 f10, e10, an210 34 a10, g10, d10 33 b10, c10, an110 32 f9, e9, an29 31 a9, g9, d9 30 b9, c9, an19 29 f8, a8, an28 28 a8, g8, d8 27 b8, c8, an18 26 f7, e7, an27 25 a7, g7, d7 24 b7, c7, an17 23 f6, e6, an26 22 a6, g6, d6 21 b6, c6, an16
b1, c1, an11 a1, g1, d1 f1, e1, an21 b2, c2, an12 a2, g2, d2 f2, e2, an22 b3, c3, an13 a3, g3, d3 f3, e3, an23 b4, c4, an14 a4, g4, d4 f4, e4, an24 b5, c5, an15 a5, g5, d5 f5, e5, an25
b1, c1, an11 a1, g1, d1 f1, e1, an21 b2, c2, an12
a2, g2, d2 10 f2, e2, an22 11 b3, c3, an13 12 a3, g3, d3 13 f3, e3, an23 14 b4, c4, an14 15 a4, g4, d4 16 f4, e4, an24 17 b5, c5, an15 18 a5, g5, d5 19 f5, e5, an25 20
ICM7232CR (PDIP) TOP VIEW
DATA CLOCK INPUT VDISP BP1 BP2 BP3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VDD 39 WRITE INPUT 38 DATA INPUT 37 DATA ACCEPTED OUTPUT 36 VSS 35 b6, c6, an16 34 a6, g6, d6 33 f6, e6, an26 32 b7, c7, an17 31 a7, g7, d7 30 f7, e7, an27 29 b8, c8, an18 28 a8, g8, d8 27 f8, a8, an28 26 b9, c9, an19 25 a9, g9, d9 24 f9, e9, an29 23 b10, c10, an110 22 a10, g10, d10 21 f10, e10, an210
b1, c1, an11 a1, g1, d1 f1, e1, an21 b2, c2, an12 a2, g2, d2 f2, e2, an22 b3, c3, an13 a3, g3, d3 f3, e3, an23 b4, c4, an14 a4, g4, d4 f4, e4, an24 b5, c5, an15 a5, g5, d5 f5, e5, an25
9-20
ICM7231, ICM7232 Functional Block Diagrams
ICM7231
D8
D7
D6
D5
D4
D3
D2
D1
f1, e1, an21 a1, g1, d1 b1, c1, an11
f2, e2, an22 a2, g2, d2 b2, c2, an12
SEGMENT LINE DRIVERS 3 WIDE OUTPUT LATCHES 9 WIDE
VDD ON CHIP DISPLAY VOLTAGE LEVEL GENERATOR
VH
VL VDISP
PIN 2 (INPUT) 9 9 9 9 9 9 9
9 COMMON LINE DRIVERS EN
BP1
BP2
DATA DECODER
DIGIT ADDRESS DECODER
BP3 ONE SHOT
DATA INPUT EN LATCHES
ADDRESS INPUT LATCHES
EN
DISPLAY TIMING GENERATOR
AN2 AN1 BD0
BD1 BD2
BD3 A0 A1 A2 CS
DATA INPUTS
ADDRESS INPUTS
NOTE: See Figure 13 for display segment connections.
9-21
ICM7231, ICM7232 Functional Block Diagrams
(Continued) ICM7232
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
f1, e1, an21 a1, g1, d1 b1, c1, an11
f2, e2, an22 a2, g2, d2 b2, c2, an12
SEGMENT LINE DRIVERS 3 WIDE OUTPUT LATCHES 9 WIDE 9 9 9 9 9 9 9 9 9 9
VDD ON CHIP VH DISPLAY VOLTAGE LEVEL V GENERATOR
L
VDISP PIN 2 (INPUT)
BP1 COMMON LINE DRIVERS EN SERIAL INPUT CONTOL LOGIC CLOCK AN1 AN2 BD0 BD1 BD2 BD3 A0 A1 A2 A3 DATA
BP2
9 DATA DECODER
DIGIT ADDRESS DECODER
BP3
DISPLAY TIMING GENERATOR
SHIFT REGISTER SHIFTS RIGHT TO LEFT ON RISING EDGE OF DATA CLOCK
DATA DATA INPUT CLOCK INPUT
WRITE DATA INPUT ACCEPTED OUTPUT
NOTE: See Figures 13 and 14 for display segment connections.
9-22
ICM7231, ICM7232
Absolute Maximum Ratings
Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Input Voltage (Note 1). . . . . . . . . . . . . . . . . . . . VSS - 0.3 VIN 6.5 Display Voltage (Note 1) . . . . . . . . . . . . . . . . . . . .0.3 VDISP +0.3
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 60 N/A CERDIP Package . . . . . . . . . . . . . . . . 50 12 Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Due to the SCR structure inherent in these devices, connecting any display terminal or the display voltage terminal to a voltage outside the power supply to the chip may cause destructive device latchup. The digital inputs should never be connected to a voltage less than -0.3V below ground, but maybe connected to voltages above VDD but not more than 6.5V above VSS . 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Power Supply Voltage, VDD
V+ = 5V +10%, VSS = 0V, TA = -25oC to 85oC, Unless Otherwise Specified TEST CONDITIONS Guaranteed Retention at 2V Current from VDD to Ground Excluding Display. VDISP = 2V VDISP Pin 2 Open VSS VDISP VDD VDISP = 2V, Current from VDD to VDISP On-Chip (Sample Test Only) See Figure 5 ICM7231, Pins 30 - 35, 37 - 39, 1 ICM7232, Pins 1, 38, 39 (Note 2) MIN 4.5 2 0 40 60 2.0 Pin 37, ICM7232, IOL = 1mA VDD = 4.5V, IOH = -500A Industrial Range 4.1 -25 TYP >4 1.6 30 1 15 75
1/ 4
MAX 5.5 100 10 VDD 30 1 120 0.8 1 0.4 +85
UNITS V V A A V A k % (VDD - VDISP) Hz V V A pF V V
oC
Data Retention Supply Voltage, VDD Logic Supply Current, IDD Shutdown Total Current, IS Display Voltage Range, VDISP Display Voltage Setup Current, IDISP DC Component of Display Signals Display Frame Rate, fDISP Input Low Level, VIL Input High Level, VIH Input Leakage, IILK Input Capacitance, CIN Output Low Level, VOL Output High Level, VOH Operating Temperature Range, TOP
Display Voltage Setup Resistor Value, RDISP One of Three Identical Resistors in String
90 0.1 5 -
AC Specifications
VDD = 5V +10% VSS = 0V, -25oC to 85oC TEST CONDITIONS (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) MIN 500 200 0 3 350 350 200 0 500 1.5 350 TYP 350 -20 -20 350 200 1.5 MAX 400 3 UNITS ns ns ns s ns ns ns ns ns s ns s ns
PARAMETER PARALLEL INPUT (ICM7231) See Figure 1 Chip Select Pulse Width, tCS Address/Data Setup Time, tDS Address/Data Hold Time, tDH Inter-Chip Select Time, tICS SERIAL INPUT (ICM7232) See Figures 2, 3 Data Clock Low Time, tCL Data Clock High Time, tCL Data Setup Time, tDS Data Hold Time, tDH Write Pulse Width, tWP Write Pulse to Clock at Initialization, tWLL Data Accepted Low Output Delay, tODL Data Accepted High Output Delay, tODH Write Delay After Last Clock, tCWS
9-23
ICM7231, ICM7232
Table of Features
TYPE NUMBER ICM7231BF ICM7232AF ICM7232BF ICM7232CR OUTPUT CODE Code B Hexadecimal Code B Code B 1 Annunciator BP1 1 Annunciator BP3 ANNUNCIATOR LOCATIONS Both Annunciators on BP3 Both Annunciators on BP3 INPUT Parallel Entry, 4-bit Data, 2-bit Annunciators, 3-bit Address Serial Entry, 4-bit Data, 2-bit Annunciators, 4-bit Address OUTPUT 8 Digits plus 16 Annunciators 10 Digits plus 20 Annunciators
Terminal Definitions
TERMINAL PIN NO. DESCRIPTION FUNCTION ICM7231 PARALLEL INPUT NUMERIC DISPLAY AN1 AN2 BD0 BD1 BD2 BD3 A0 A1 A2 CS 30 31 32 33 34 35 37 38 39 1 Most Significant Data Input Strobe/Chip Select (Note 2) Trailing (Positive going) edge latches data, causes data input to be decoded and sent out to addressed digit Most Significant Least Significant 3-bit Digit Address Inputs Input Address (See Table 2) Annunciator 1 Control Bit Annunciator 2 Control Bit Least Significant 4-bit Binary Data Inputs High = ON Low = OFF Input Data (See Table 1) See Table 3 HIGH = Logical One (1) LOW = Logical Zero (0)
ICM7232 SERIAL DATA AND ADDRESS INPUT Data Input WRITE Input 38 39 Data+ Address Shift Register Input Decode, Output, and Reset Strobe HIGH = Logical One (1) LOW = Logical Zero (O) When DATA ACCEPTED Output is LOW, positive going edge of WRITE causes data in shift register to be decoded and sent to addressed digit, then shift register and control logic to be reset. When DATA ACCEPTED Output is HIGH, positive going edge of WRITE triggers reset only. Positive going edge advances data in shift register. ICM7232: Eleventh edge resets shift register and control logic. Output LOW when correct number of bits entered into shift register.
Data Clock Input DATA ACCEPTED Output ALL DEVICES Display Voltage VDlSP Common Line Driver Outputs Segment Line Driver Outputs VDD VSS
1 37
Data Shift Register and Control Logic Clock Handshake Output
2
Negative end of on-chip resistor string Display voltage control. When open (or less than 1V from VDD) chip used to generate intermediate voltage is shutdown; oscillator stops, all display pins to VDD . levels for display. Shutdown Input. Drive display commons, or rows
3, 4, 5
6 - 29 6 - 35 40 36
(On ICM7231) (On ICM7232) Chip Positive Supply Chip Negative Supply
Drive display segments, or columns.
NOTES: 1. For Design reference only, not 100% tested. 2. CS has a special "mid-level" sense circuit that establishes a test mode if it is held near 3V for several ms. Inadvertent triggering of this mode can be avoided by pulling it high when inactive, or ensuring frequent activity.
9-24
ICM7231, ICM7232 Timing Diagrams
tCS CS INPUT tICS
DATA ADDRESS INPUT
ADDRESS AND DATA INPUTS VALID tDH
ADDRESS AND DATA INPUTS VALID
tDS
DO NOT CARE
FIGURE 1. ICM7231 INPUT TIMING DIAGRAM
DATA CLOCK INPUT (PER BIT OF DATA) DATA INPUT
tCI 1 2
ELEVENTH CLOCK WITH NO WRITE PULSE RESETS SR + LOGIC tCI 3 8 9 10 tODL
AN1 DATA VALID
AN2 DATA VALID
BD0 DATA VALID
A1 DATA VALID
A2 DATA VALID
A3 DATA VALID
tDS tDH DATA ACCEPTED OUTPUT tWLL tWP WRITE INPUT RESETS SHIFT REGISTER AND INPUT CONTROL LOGIC WHEN DATA ACCEPTED HIGH tCWS tODL
tODH
tWP
DO NOT CARE
DECODES AND STORES DATA, RESETS SHIFT REGISTER AND LOGIC WHEN DATA ACCEPTED IS LOW
FIGURE 2. ICM7232 ONE DIGIT INPUT TIMING DIAGRAM, WRITING BOTH ANNUNCIATORS
9-25
ICM7231, ICM7232 Timing Diagrams
AN1 ENTER FIRST AN2 BD0 BD1 BD2 BD3 A0 A1 A2 A3 ENTER LAST
ICM7232 WRITE ORDER
tCI tCI DATA CLOCK INPUT tDS DATA INPUT
BD0 DATA VALID
1
2
3
7
8
tDH
BD1 DATA VALID BD2 DATA VALID A2 DATA VALID A3 DATA VALID
tODI DATA ACCEPTED OUTPUT tODH tWLL tWP WRITE INPUT RESETS SHIFT REGISTER AND INPUT CONTROL LOGIC WHEN DATA ACCEPTED HIGH DECODES AND STORES DATA, RESETS SHIFT REGISTER AND LOGIC WHEN DATA ACCEPTED IS LOW tCWS tWP
DO NOT CARE
FIGURE 3. ICM7232 INPUT TIMING DIAGRAM, LEAVING BOTH ANNUNCIATORS OFF
ICM7231 Family Description
The ICM7231 drives displays with 8 seven-segment digits with two independent annunciators per digit, accepting six data bits and three digit address bits from parallel inputs controlled by a chip select input. The data bits are subdivided into four binary code bits and two annunciator control bits. The ICM7232 drives 10 seven-segment digits with two independent annunciators per digit. To write into the display, six bits of data and four bits of digit address are clocked serially into a shift register, then decoded and written to the display. Input levels are TTL compatible, and the DATA ACCEPTED output on the serial input devices will drive one LSTTL load. The intermediate voltage levels necessary to drive the display properly are generated by an on-chip resistor string, and the output of a totally self-contained on-chip oscillator is used to generate all display timing. All devices in this family have been fabricated using Intersil' MAXCMOS(R) process and all inputs are protected against static discharge. Triplexed (1/3 Multiplexed) Liquid Crystal Displays Figure 4 shows the connection diagram for a typical 7-segment display with two annunciators such as would be used with an ICM7231 or ICM7232 numeric display driver. Figure 5 shows the voltage waveforms of the common lines
MAXCMOS(R) is a registered trademark of Intersil Corporation.
and one segment line, chosen for this example to be the "a, g, d" segment line. This line intersects with BP1 to form the "a" segment, BP2 to form the "g" segment and BP3 to form the "d" segment. Figure 5 also shows the waveform of the "a, g, d" segment line for four different ON/OFF combinations of the "a", "g" and "d" segments. Each intersection (segment or annunciator) acts as a capacitance from segment line to common line, shown schematically in Figure 6. Figure 7 shows the voltage across the "g" segment for the same four combinations of ON/OFF segments used in Figure 5.
SEGMENT LINES BP1
a f g e an2 d b c an1
a f g e d an2 an1
SEGMENT LINE CONNECTIONS
b c
BP2
BP3 BACKPLANE CONNECTIONS
FIGURE 4. CONNECTION DIAGRAMS FOR TYPICAL 7-SEGMENT DISPLAYS
9-26
ICM7231, ICM7232
1 2 3 1 2 3
VDD BP1 VH VL VDISP BP3 VDD BP2 VH VL VDISP VDD BP3 VH VL VDISP VDD SEGMENT LINE ALL OFF VH VL VDISP VDD VH VL VDISP TYPICAL SEGMENT LINE WAVEFORMS a, g ON d OFF 0 -VP +VP COMMON LINE WAVEFORMS VP BP2 BP1 SEGMENT LINES
f e an2
a g d
b c an1
FIGURE 6. DISPLAY SCHEMATIC VP = (V+) - VDISP
1 2 3 1 2 3
+VP ON CHIP RESISTOR STRING VDD
ALL OFF
0
~75k
VH
-VP
~75k
VL
VP V RMS = ------- = V RMS OFF 3
~75k
PIN 2 VDISP INPUT a SEGMENT ON a, d OFF
+VP
a SEGMENT
ON a, d OFF
0
a, g ON
d OFF
VDD VH VL VDISP
-VP VDD ALL ON VH VL
11 VP V RMS = ---------- x ------- = V RMS ON 3 3
NOTES:
VDISP +VP
1. 1, 2, 3, - BP High with Respect to Segment. 2. 1, 2, 3, - BP Low with Respect to Segment. 3. BP1 Active during 1, and 1. 4. BP2 Active during 2, and 2. 5. BP3 Active during 3, and 3. FIGURE 5. DISPLAY VOLTAGE WAVEFORMS
ALL ON
0
-VP
The degree of polarization of the liquid crystal material and thus the contrast of any intersection depends on the RMS voltage across the intersection capacitance. Note from Figure 7 that the RMS OFF voltage is always VP/3 and that the RMS ON voltage is always 1.92VPEAK /3. For a 1/3 multiplexed LCD, the ratio of RMS ON to OFF voltages is fixed at 1.92, achieving adequate display contrast with this ratio of applied RMS voltage makes some demands on the liquid crystal material used.
V RMS ON 11 Voltage Contrast Ratio = ----------------------------- = ---------- = 1.92 V RMS OFF 3 NOTES: 1. 1, 2, 3, - BP High with Respect to Segment. 2. 1, 2, 3, - BP Low with Respect to Segment. 3. BP1 Active during 1, and 1. 4. BP2 Active during 2, and 2. 5. BP3 Active during 3, and 3. FIGURE 7. VOLTAGE WAVEFORMS ON SEGMENT g(VG)
9-27
ICM7231, ICM7232
Figure 8 shows the curve of contrast versus applied RMS voltage for a liquid crystal material tailored for VPEAK = 3.1V, a typical value for 1/3 multiplexed displays in calculators. Note that the RMS OFF voltage VPEAK /3 1V is just below the "threshold" voltage where contrast begins to increase. This places the RMS ON voltage at 2.1V, which provides about 85% contrast when viewed straight on.
0+
specifying displays the following must be kept in mind: liquid crystal material, polarizer, and seal materials. A more important effect of temperature is the variation of threshold voltage. For typical liquid crystal materials suitable for multiplexing, the peak voltage has a temperature coefficient of -7 to -14mV/oC. This means that as temperature rises, the threshold voltage goes down. Assuming a fixed value for VP when the , threshold voltage drops below VPEAK/3 OFF segments begin to be visible. Figure 9 shows the temperature dependence of peak voltage for the same liquid crystal material of Figure 8.
6 5
0-
90 80 70 CONTRAST (%) 60 50 40 30 20 10 0 0
TA = 25oC
= -10o
PEAK VOLTAGE
100
PEAK VOLTAGE FOR 90% CONTRAST (ON)
=0
4 3 2 1 PEAK VOLTAGE FOR 10% CONTRAST (OFF)
= -30o
VOFF = 1.1VRMS
= +10o
0 -10 VON = 2.1V
0
10 20 30 40 AMBIENT TEMPERATURE (oC)
50
FIGURE 9. TEMPERATURE DEPENDENCE OF LC THRESHOLD
1
2 3 APPLIED VOLTAGE (VRMS)
4
FIGURE 8. CONTRAST vs APPLIED RMS VOLTAGE
All members of the ICM7231 and ICM7232 family use an internal resistor string of three equal value resistors to generate the voltages used to drive the display. One end of the string is connected on the chip to VDD and the other end (user input) is available at pin 2 (VDISP) on each chip. This allows the display voltage input (VDISP) to be optimized for the particular liquid crystal material used. Remember that VPEAK = VDD - VDISP and should be three times the threshold voltage of the liquid crystal material used. Also it is very important that pin 2 never be driven below VSS . This can cause device latchup and destruction of the chip. Temperature Effects and Temperature Compensation The performance of the LCD material is affected by temperature in two ways. The response time of the display to changes of applied RMS voltage gets longer as the display temperature drops. At very low temperatures (-20oC) some displays may take several seconds to change a new character after the new information appears at the outputs. However, for most applications above 0oC this will not be a problem with available multiplexed LCD materials, and for low-temperature applications, high-speed liquid crystal materials are available. At high temperature, the effect to consider deals with plastic materials used to make the polarizer. Some polarizers become soft at high temperatures and permanently lose their polarizing ability, thereby seriously degrading display contrast. Some displays also use sealing materials unsuitable for high temperature use. Thus, when
For applications where the display temperature does not vary widely, VPEAK may be set at a fixed voltage chosen to make the RMS OFF voltage, VPEAK /3, just below the threshold voltage at the highest temperature expected. This will prevent OFF segments turning ON at high temperature (this at the cost of reduced contrast for ON segments at low temperatures). For applications where the display temperature may vary to wider extremes, the display voltage VDISP (and thus VPEAK) may require temperature compensation to maintain sufficient contrast without OFF segments becoming visible. Display Voltage and Temperature Compensation These circuits allow control of the display peak voltage by bringing the bottom of the voltage divider resistor string out at pin 2. The simplest means for generating a display voltage suitable to a particular display is to connect a potentiometer from pin 2 to VSS as shown in Figure 10. A potentiometer with a maximum value of 200k should give sufficient range of adjustment to suit most displays. This method for generating display voltage should be used only in applications where the temperature of the chip and display won't vary more than 5oC (9oF), as the resistors on the chip have a positive temperature coefficient, which will tend to increase the display peak voltage with an increase in temperature. The display voltage also depends on the power supply voltage, leading to tighter tolerances for wider temperature ranges.
9-28
ICM7231, ICM7232
OPEN
200k 10nF
2 VDISP 40 ICM7231 ICM7232 36
+5
FIGURE 10. SIMPLE DISPLAY VOLTAGE ADJUSTMENT
Figure 11A shows another method of setting up a display voltage using five silicon diodes in series. These diodes, 1N914 or equivalent, will each have a forward drop of approximately 0.65V, with approximately 20A flowing through them at room temperature. Thus, 5 diodes will give 3.25V, suitable for a 3V display using the material properties shown in Figures 4 and 5. For higher voltage displays, more diodes may be added. This circuit provides reasonable temperature compensation, as each diode has a negative temperature coefficient of -2mV/oC; five in series gives -10mV/oC, not far from optimum for the material described. The disadvantage of the diodes in series is that only integral multiples of the diode voltage can be achieved. The diode voltage multiplier circuit shown in Figure 11B allows finetuning the display voltage by means of the potentiometer; it likewise provides temperature compensation since the temperature coefficient of the transistor base-emitter junction (about -2mV/oC) is also multipled. The transistor should have a beta of at least 100 with a collector current of 10A. The inexpensive 2N2222 shown in the figure is a suitable device.
VDD
For battery operation, where the display voltage is generally the same as the battery voltage (usually 3 - 4.5V), the chip may be operated at the display voltage, with VDlSP connected to VSS . The inputs of the chip are designed such that they may be driven above VDD without damaging the chip. This allows, for example, the chip and display to operate at a regulated 3V, and a microprocessor driving its inputs to operate with a less well controlled 5V supply. (The inputs should not be driven more than 6.5V above GND under any circumstances.) This also allows temperature compensation with the ICL7663S, as shown in Figure 12. This circuit allows independent adjustment of both voltage and temperature compensation.
+5V VIN + VOUT1 LOGIC SYSTEM PROCESSOR, ETC. VOUT2 ICL7663S VSET 300k VTC GND 2.7M VDISP GND 1.8M VDD
ICM7233
DATA BUS
FIGURE 12. FLEXIBLE TEMPERATURE COMPENSATION
Description Of Operation
Parallel Input Of Data And Address (ICM7231) The parallel input structure of the ICM7231 device is organized to allow simple, direct interfacing to all microprocessors, (see the Functional Block Diagram). In the ICM7231, address and data bits are written into the input latches on the rising edge of the Chip Select input. The rising edge of the Chip Select also triggers an on-chip pulse which enables the address decoder and latches the decoded data into the addressed digit/character outputs. The timing requirements for the parallel input device are shown in Figure 1, with the values for setup, hold, and pulse width times shown in the AC Specifications section. Note that there is a minimum time between Chip Select pulses; this is to allow sufficient time for the on-chip enable pulse to decay, and ensures that new data doesn't appear at the decoder inputs before the decoded data is written to the outputs.
40 36 ICM7231 ICM7232 +5
1N914 DIODES
2 VDISP
40 36
+5
ICM7231 ICM7232 40k 10nF
FIGURE 11A. STRING OF DIODES
VDD
2 VDISP 200k POTENTIOMETER 2N2222
Serial Input Of Data And Address (ICM7232) The ICM3232 trades six pins used as data inputs on the ICM7231 for six more segment lines, allowing two more 9-segment digits. This is done at the cost of ease in interfacing, and requires that data and address information be entered serially. Refer to Functional Block Diagram and timing diagrams, Figures 2 and 3. The interface consists of four pins: DATA Input, DATA CLOCK Input, WRITE Input and DATA ACCEPTED Output. The data present at the DATA Input is clocked into a shift register on the rising edge of the
40k
10nF
FIGURE 11B. TRANSISTOR-MULTIPLIER FIGURE 11. DIODE-BASED TEMPERATURE COMPENSATION
9-29
ICM7231, ICM7232
DATA CLOCK Input signal, and when the correct number of bits has been shifted into the shift register (8 in the ICM7232), the DATA ACCEPTED Output goes low. Following this, a low-going pulse at the WRITE input will trigger the chip to decode the data and store it in the output latches of the addressed digit/character. After the data is latched at the outputs, the shift register and the control logic are reset, returning the DATA ACCEPTED Output high. After this occurs, a pulse at the WRITE input will not change the outputs, but will reset the control logic and shift register, assuring that each data bit will be entered into the correct position in the shift register depending on subsequent DATA CLOCK inputs. The shift register and control logic will also be reset if too many DATA CLOCK INPUT edges are received; this prevents incorrect data from being decoded. In the ICM7232, the eleventh clock resets the shift register and control logic. The recommended procedure for entering data is shown in the serial input timing diagram, Figure 2. First, when DATA ACCEPTED is high, send a WRITE pulse. This resets the shift register and control logic and initializes the chip for the data input sequence. Next clock in the appropriate number of correct data and address bits. The DATA ACCEPTED Output may be monitored if desired, to determine when the chip is ready to output the decoded data. When the correct number of bits has been entered, and the DATA ACCEPTED Output is low, a pulse at WRITE will cause the data to be decoded and stored in the latches of the addressed digit/character. The shift register and control logic are reset, causing DATA ACCEPTED to return high, and leaving the chip ready to accept data for the next digit/character. Note that for the ICM7232 the eleventh clock resets the shift register and control logic, but the DATA ACCEPTED Output goes low after the eighth clock. This allows the user to abbreviate the data to eight bits, which will write the correct character to the 7-segment display, but will leave the annunciators off, as shown in Figure 3. If only AN2 is to be turned on, nine bits are clocked in; if AN1 is to be turned on, all ten bits are used. The DATA ACCEPTED Output will drive one low-power Schottky TTL input, and has equal current drive capability pulling high or low. Note that in the serial Input devices, it is possible to address digits/characters which don't exist. As shown in Table 2 when an incorrect address is applied together with a WRITE pulse, none of the outputs will be changed. Display Fonts and Output Codes The standard versions of the ICM7231 and ICM7232 chips are programmed to drive a 7-segment display plus two annunciators per digit. See Table 3 for annunciator input controls. The "A" and "B" suffix chips place both annunciators on BP3. The display connections for one digit of this display are shown in Figure 13. The "A" devices decode the input data into a hexadecimal 7-segment output, while the "B" devices supply Code B outputs (see Table 1). The "C" devices place the left hand annunciator on BP1 and the right hand annunciator (usually a decimal point) on BP3. (See Figure 14). The "C" devices provide only a "Code B" output for the 7 segments.
1 0 1 0 TABLE 1. BlNARY DATA DECODING ICM7231 AND ICM7232 CODE INPUT BD3 0 BD2 0 BD1 0 BD0 0 DISPLAY OUTPUT HEX CODE B
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
BLANK
9-30
ICM7231, ICM7232
TABLE 2. ADDRESS DECODING (ICM7231 AND ICM7232) DISPLAY OUTPUT DIGIT SELECTED D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 NONE NONE
SEGMENT LINES
)
SEGMENT LINES
CODE INPUT ICM7232 ONLY A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SEGMENT LINE CONNECTIONS
a
BP1
f g e an2 d
b c an1
BP2
BP3 BACKPLANE CONNECTIONS
FIGURE 13. ICM7231 AND ICM7232 DISPLAY FONTS ("A" AND "B" SUFFIX VERSIONS
NONE NONE NONE NONE
(NOTE 1)
TABLE 3. ANNUNClATOR DECODING CODE INPUT
SEGMENT LINE CONNECTIONS SEGMENT LINES BP1 (NOTE 1) BP2
DISPLAY OUTPUT ICM7231C ICM7232C an2 ANNUNCIATOR BP1 an1 ANNUNClATOR BP3 NOTE:
AN2 0
AN1 0
ICM7231A AND ICM7231B ICM7232A AND ICM7232B BOTH ANNUNCIATORS ON BP3
an2
a f g e d c an1 b
BP3 BACKPLANE CONNECTIONS
0
1
1. Annunciators can be: STOP , GO , , -arrows that point to information printed around the display opening etc., whatever the designer display opening etc., whatever the designer chooses to incorporate in the liquid crystal display. FIGURE 14. ICM7231 DISPLAY FONTS ("C" SUFFIX VERSIONS)
Compatible Displays
1 0
Compatible displays are manufactured by: G.E. Displays Inc., Beechwood, Ohio (216) 831-8100 (#356E3R99HJ) Epson America Inc., Torrance CA (Model Numbers LDB726/7/8). Seiko Instruments USA Inc., Torrance CA (Custom Displays) Crystaloid, Hudson, OH
1
1
9-31
ICM7231, ICM7232 Typical Applications
PERIOD INTERVAL UNIT TEST FREQ. RATIO FREQUENCY
OVER RANGE
27
ICM7231CF BD0 - 3 AN2 AN1 A0 A1 A2 CS
INPUT A
BCD ICM7226A
DP FUNCTION +5V RANGE
INPUT B D1 - D8
Q0
Q1
Q2
E1
V+ 1F
10K
CD4532 D0 - D7
GS
NOTE: The annunciators show function and the decimal points indicate the range of the current operation. the system can be efficiently battery operated. FIGURE 15. 10MHz FREQUENCY/PERIOD POINTER WITH LCD DISPLAY
9-32
ICM7231, ICM7232 Typical Applications
D8
(Continued)
D7 D6 D5 D4 D3 D2 D1 COM 1 COM 2 COM 3
XYZ
XYZ
XYZ
XYZ
XYZ
XYZ
XYZ
XYZ
ICM7231AF AND ICM7231BF TOP VIEW
TO INPUT
FIGURE 16. "FORWARD" PIN ORIENTATION AND DISPLAY CONNECTIONS
D10 SELECT
D9 NO
D8 FORWARD
D7
D6
D5
D4
D3 STOP
D2 WAIT
D1 COM 1 GO COM 2 COM 3
XYZ
XYZ
XYZ
XYZ
XYZ
XYZ
XYZ
XYZ
XYZ
XYZ
ICM7232CR TOP VIEW
PCB TRACES UNDER PACKAGE
TO INPUT
FIGURE 17. "REVERSE" PIN ORIENTATION AND DISPLAY CONNECTIONS
9-33
ICM7231, ICM7232
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
9-34

▲Up To Search▲

Price & Availability of ICM7231

	To Download ICM7231 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .